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| OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS The SN54 / 74LS540 and SN54 / 74LS541 are octal buffers and line drivers with the same functions as the LS240 and LS241, but with pinouts on the opposite side of the package. These device types are designed to be used as memory address drivers, clock drivers and bus-oriented transmitters / receivers. These devices are especially useful as output ports for the microprocessors, allowing ease of layout and greater PC board density. SN54/74LS540 SN54/74LS541 OCTAL BUFFER / LINE DRIVER WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY * * * * Hysteresis at Inputs to Improve Noise Margin PNP Inputs Reduce Loading 3-State Outputs Drive Bus Lines Inputs and Outputs Opposite Side of Package, Allowing Easier Interface to Microprocessors * Input Clamp Diodes Limit High-Speed Termination Effects LOGIC AND CONNECTION DIAGRAMS DIP (TOP VIEW) VCC 20 19 20 1 J SUFFIX CERAMIC CASE 732-03 SN54 / 74LS540 18 17 16 15 14 13 12 11 20 1 N SUFFIX PLASTIC CASE 738-03 1 2 3 4 5 6 7 8 9 10 GND 20 1 DW SUFFIX SOIC CASE 751D-03 VCC 20 19 SN54 / 74LS541 18 17 16 15 14 13 12 11 ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC 1 2 3 4 5 6 7 8 9 10 GND GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 12 - 15 12 24 Unit V C mA mA FAST AND LS TTL DATA 5-1 SN54/74LS540 * SN54/74LS541 BLOCK DIAGRAM LS540 (1) E1 (19) E2 (2) (18) (1) E1 (19) E2 (2) (18) LS541 INPUTS E1 Y1 L H X L E2 L X H L D H X X L OUTPUTS LS540 L Z Z H LS541 H Z Z L D1 D2 D3 D4 D5 D6 D7 D8 Y1 D1 D2 D3 D4 D5 D6 D7 D8 (3) (4) (5) (6) (7) (8) (9) (17) (16) (15) (14) (13) Y2 Y3 Y4 Y5 Y6 (3) (4) (5) (6) (7) (8) (9) (17) (16) (15) (14) (13) Y2 Y3 Y4 Y5 Y6 L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial Z = High Impedance (12) Y7 (11) Y8 (12) Y7 (11) Y8 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54, 74 Output HIGH Voltage 54, 74 54, 74 VOL VT+-VT- IOZH IOZL IIH IIL IOS Output LOW Voltage 74 Hysteresis Output Off Current HIGH Output Off Current LOW Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total, Output HIGH LS540 LS541 ICC LS540 Total, Total Output LOW LS541 LS540 LS541 - 40 - 0.2 - 225 25 32 45 52 52 55 0.2 0.35 0.4 20 - 20 20 0.5 V V A A A mA mA mA mA mA mA mA mA mA VCC = MAX 2.0 0.25 0.4 V V 2.4 - 0.65 3.4 0.8 - 1.5 V V Min 2.0 0.7 V Typ Max Unit Ui V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = - 3.0 mA VCC = MIN, IOH = MAX, VIL = 0.5 V IOL = 12 mA IOL = 24 mA VCC = MIN VCC = MAX, VOUT = 2.7 V VCC = MAX, VOUT = 0.4 V VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = VCC MIN, VIN = VIL or VIH per Truth Table Total Output 3-State Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-2 SN54/74LS540 * SN54/74LS541 AC CHARACTERISTICS (TA = 25C) Limits Symbol S bl tPLH tPLH tPHL tPHL tPZH Output Enable Time p to HIGH Level Output Enable Time p to LOW Level Output Disable Time p to HIGH Level Output Disable Time p to LOW Level Propagation Delay, P p g i D l y, Data to Output Parameter P LS540 LS541 LS540 LS541 LS540 LS541 LS540 LS541 LS540 LS541 LS540 LS541 Min Typ 9.0 12 12 12 15 15 20 20 10 10 15 15 Max 15 15 ns 15 18 25 ns 32 38 ns 38 18 ns 18 25 ns 29 CL = 5.0 pF 50 F VCC = 5.0 V 50 CL = 45 pF RL = 667 Unit Ui Test C di i T Conditions tPZL tPHZ tPLZ AC WAVEFORMS VCC VIN 1.3 V tPLH VOUT 1.3 V 1.3 V tPHL 1.3 V SW1 RL Figure 1 TO OUTPUT UNDER TEST VIN 1.3 V tPLH VOUT 1.3 V 1.3 V tPHL 1.3 V CL* 5 k SW2 Figure 2 VE VE VOUT 1.5 V tPZL 1.5 V 1.5 V tPLZ 1.5 V VOL 0.5 V SYMBOL tPZH SWITCH POSITIONS SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed Figure 3 VE 1.5 V VE VOUT tPZH 1.5 V 1.5 V tPHZ VOH 1.5 V 0.5 V tPZL tPLZ tPHZ Figure 4 Figure 5 FAST AND LS TTL DATA 5-3 |
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